As the integrated circuit device scale is further reduced, there are a few strategies to continuously enhance semiconductor device performance. One strategy is strain engineering. Performance benefits are achieved by modulating strain in the transistor channel, which enhances electron mobility (or hole mobility) and thereby conductivity through the channel.
In CMOS technologies, PMOS and NMOS respond differently to different types of strain. Specifically, PMOS performance is best served by applying compressive strain to the channel, whereas NMOS receives benefit from tensile strain. For example, SiGe (Si1-xGex), consisting of any molar ratio of silicon and germanium such as Si0.3Ge0.7, is commonly used as a semiconductor material in integrated circuits (ICs) as a strain-inducing layer (i.e. stressor) for strained silicon in CMOS transistors.
Strained silicon is a layer of silicon in which the silicon atoms are stretched beyond their normal interatomic distance. For example, this can be accomplished by putting the layer of silicon over a substrate of silicon germanium (SiGe). As the atoms in the silicon layer align with the atoms of the underlying silicon germanium layer which are arranged farther apart with respect to those of a bulk silicon crystal, the links between the silicon atoms become stretched—thereby leading to strained silicon.
Another strategy is using multigate devices. A multigate device or Multigate Field Effect Transistor (MuGFET) refers to a MOSFET that incorporates more than one gate into a single device. The multiple gates may be controlled by a single gate electrode where the multiple gate surfaces act electrically as a single gate, or by independent gate electrodes. A multigate device employing independent gate electrodes is sometimes called a Multiple Independent Gate Field Effect Transistor (MIGFET).
In a multigate device, the channel is surrounded by more than one gate on multiple surfaces, allowing more effective suppression of “off-state” leakage current. Multiple gates also allow enhanced current in the “on” state, also known as drive current. The higher contrast between on/off states and reduced leakage current results in lower power consumption and enhanced device performance. Non-planar devices are also more compact than conventional planar transistors, enabling higher transistor density that translates to smaller overall integrated circuits.
Despite the above strategies, still further improvements and better performances including higher carrier mobility are desirable. More particularly, higher strain by SiGe/Ge strained-device is desirable, but it is difficult to make a high tensile Ge device. Also, a poor interface between gate dielectric and Ge of NMOS device is problematic.
Accordingly, new structures and methods for better device performance including higher carrier mobility and better interface between gate dielectric and Ge of an NMOS device are desired.